Combining LDPC, turbo and Viterbi decoders: Benefits and costs

In this paper we present a detailed analysis into the benefits and costs of merging decoders for different channel code types such as convolutional, turbo and LDPC codes. An ASIP (application-specific instruction set processor)-based framework for multi-code forward error correction (FEC) architectures is applied to implement three dedicated decoders for convolutional, turbo and LDPC codes respectively as well as one decoder capable of decoding all three. Synthesis results and performance estimations for all architectures are presented and used to draw a clear and fair comparison between single-mode and multi-mode decoders.