An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS

This paper introduces an experimental test-flow for evaluating the susceptibility of SRAM based FPGA designs to SEU (Single Event Upsets). Using this method it is possible to cover both SEUs and MBU (Multiple Bit Upsets) in the configuration memory of Xilinx FPGAs for applications based on tiny soft microprocessors. The introduced test-flow imposes a minimal effort to the system developer and achieves a good estimation on the percentage of critical bits in the configuration memory of a design. This flow is executed for a design using multiple tiny soft microprocessors and the reliability values extracted by the test-flow are compared to non-experimental estimation techniques.