Modeling of a DMOS transistor up to very high temperatures

The emerging smart power BCD technologies allow smaller device sizes hence, under the same operating conditions, the device must dissipate the same amount of power on a much smaller area, which leads to a more pronounced self - heating effect. Therefore, accurate prediction of heat dissipation in the DMOS structure, up to thermal runaway, is necessary. We have designed a test structure capable of uniformly heating a small area VDMOS device up to 500°C. In this paper we validate the test structure by modeling the behavior of the DMOS transistor up to very high temperatures.