Tag simplification: Achieving power efficiency through reducing the complexity of the wakeup logic

Contemporary microprocessor cores employ out-of-order execution in order to boost performance. One of the artifacts of the out-of-order execution is the Content Addressable Memory (CAM) cells that allow comparison of the incoming data with the stored value. Many components use these cells inside the processor such as the Issue Queue (IQ), which holds the instructions until their source operands are ready. These processor components receive lookup data each cycle and dissipate significant energy for the comparison operation. In this paper we propose a methodology to remove the capacitive load from the lookup buses and reduce the complexity of the comparison circuitry inside the CAM logic. For demonstration purposes we show the design of a new implementation of the IQ that allows the designers to transfer the complexity to the frontend stages of the processor. Our design reduces the dynamic energy dissipation of the CAM array inside the issue queue 15% with virtually no impact on performance.