Analysis of impact of FPGA routing architecture parameters on area and delay

FPGAs are increasingly replacing more expensive microprocessors and ASICs in a wide variety of applications. Their performance is limited mainly by the characteristics of the routing network. This paper presents a detailed study of the influence of the parameters defining an FPGA routing network on the routing area, the critical path delay, and the channel width required to place and route benchmark circuits. The goal was to find the set of parameter values providing maximal performance of the routing network. The results have shown that the trade-offs are inevitable.