DocumentCode :
3645907
Title :
A general purpose Ethernet based readout data acquisition system
Author :
Bartosz Mindur;Lukasz Jachymczyk
Author_Institution :
Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Krakó
fYear :
2011
Firstpage :
800
Lastpage :
806
Abstract :
A flexible dedicated readout system is one of the most important part of any kind of dedicated detection system, especially for its testing phase as well as when the final system is ready for implementation. An obvious choice is to use a FPGA (apart from dedicated front-end electronics) as a first stage of data storage and processing element. Furthermore the FPGA has to prepare and transfer the incoming/processed data to the host PC. The implementation of the data exchange can be a problem, especially for small groups of developers, who have an option to buy a general solution with its limitations and a price, or to do time-consuming development of their own system practically from scratch. This paper presents a FPGA based general purpose readout solution which lies in between the two opposite approaches. Presented system uses a FPGA mezzanine board equipped with Ethernet Gigabit connection to PC. The FPGA FIFO based readout of a digital data stream is packed directly into the Ethernet frames and send to the destination PC using point-to point connection. The standard Ethernet frames are used in this design, additionally equipped with one byte carrying information on data type. When a high throughput is needed the data type is employed to prioritize them. This moderately simple but very powerful interface is relatively easy to be implemented in many applications [1]. The custom approach chosen for FPGA implementation causes a need to prepare dedicated software suite to process all incoming data in the PC side. The developed software package is called EPPRO (Ethernet Packet PROxy) since it exploits special Ether net frames for data exchange. The core part of EPPRO is a Linux kernel module, responsible for data reception/transmission and dispatching, taking into account their types to filter and prioritize the incoming packets. Overall performance of the whole system has been evaluated in respect to its throughput and reliability, presented test results confirm that all of the design goals have been fulfilled.
Keywords :
"Field programmable gate arrays","Sockets","Indexes","Payloads","Clocks","Decoding","Random access memory"
Publisher :
ieee
Conference_Titel :
Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE
ISSN :
1082-3654
Print_ISBN :
978-1-4673-0118-3
Type :
conf
DOI :
10.1109/NSSMIC.2011.6154542
Filename :
6154542
Link To Document :
بازگشت