Yield Modeling for Error Tolerant and Partially Defect Tolerant Arrays

All defect-tolerant techniques increase area consumption due to the introduction of redundancy. In order to ensure that any proposed defect-tolerant technique will be cost effective, it is necessary to develop a yield model. The goal of this paper is yield modeling for two defect-tolerant techniques, namely Error Tolerant and Partially Defect Tolerant technique. In order to evaluate and compare the techniques, mathematical models for Error Tolerance, and two variations of Partial Defect Tolerance technique will be derived. The models will be described in detail and illustrated on a generic architecture. It will be shown that both TMR and spare component techniques, used as a basis in Partial Defect Tolerance, can be effective in yield improvement. The models will be illustrated on the example of bit-plane semi-systolic FIR filter. Using proposed models it will be shown that the techniques can be well exploited in the environments that have high defect rates, such as nanotechnology.