Implementation of a FPGA-based overlap-add filter

In this research, an efficient pipelined overlap-add filter is designed for the linear convolution of the streaming data. The designed filter uses the overlap-add method and modified radix- 4 architecture for the zero-padded input data. We used several techniques in order to decrease the hardware resources for the proposed design. Firstly, FFT (Fast Fourier Transform) resources are shared between the two FFT units used for the overlap-add method. Second, bit-reversed inputs are used for inverse FFT operation. The target device for the implementation is a Xilinx Virtex-5 FPGA. The architecture yields similar accuracy and throughput with the cost of less hardware resources than the designs using the commercial FFT IP(Intellectual Property) cores.