FPGA implementation of cubic spline interpolation method for empirical mode decomposition

In this work, cubic spline interpolation method is implemented on a field programmable gate array (FPGA) to be used for real time empirical mode decomposition. Different from the software implementation of the method, in the hardware implementation, a hardware architecture is designed with performance and resource usage under consideration. According to the experimental results, the hardware architecture performed the computation approximately 900 times faster compared to the software implementation. The designed hardware architecture is successfully integrated with empirical mode decomposition (EMD) method which generally is utilized as a building block of classification methods proposed in the literature.