• DocumentCode
    3646968
  • Title

    Improving the iterative power of resynthesis

  • Author

    Petr Fišer;Jan Schmidt

  • Author_Institution
    Faculty of Information Technology, Czech Technical University in Prague, Czech Republic
  • fYear
    2012
  • fDate
    4/1/2012 12:00:00 AM
  • Firstpage
    30
  • Lastpage
    33
  • Abstract
    We present a method of improving the iterative power of resynthesis of Boolean networks in this paper. In principle it is based on iterative resynthesis of parts of the network, instead of processing the network as a whole. The parts are randomly selected, thus more variability is introduced. The process is scalable, at least as much as the state-of-the-art. We show that our method performs better than the academic state-of-the-art, the ABC tool from Berkeley. This is documented by extensive experiments on LGSynth´93 benchmark circuits.
  • Keywords
    "Logic gates","Benchmark testing","Standards","Convergence","Niobium","Iterative methods","Optimization"
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
  • Print_ISBN
    978-1-4673-1187-8
  • Type

    conf

  • DOI
    10.1109/DDECS.2012.6219019
  • Filename
    6219019