A systematic M safe-error detection in hardware implementations of cryptographic algorithms

This paper presents a procedure that checks whether a hardware implementation of a cryptographic algorithm is vulnerable to M safe-error attacks. It takes a registertransfer level (RTL) description of a design as an input and exposes the exact timing and a memory element that is a possible target of the attack. As a proof of concept, the presented procedure is applied to a hardware implementation of the Montgomery Powering Ladder, an exponentiation algorithm commonly used in public-key cryptography.