Design solutions for securing SRAM cell against power analysis

Side channel attacks exploit physical imperfections of hardware to circumvent security features achieved by mathematically secure protocols and algorithms. This is achieved by monitoring physical quantities, usually power consumption or electromagnetic radiation, which contain information about the secret data. As a countermeasure, several circuit styles have been proposed for designing side-channel resistant logic gates and flip-flops. However, little effort has been made to develop secure memory arrays. An SRAM cell with 8 transistors has been proposed in order to obtain power analysis resistance by using a dual-rail precharge principle, the same technique used in various secure logic styles. In this paper we look into the practical aspects of this cell such as noise margins, layout strategy and read current. In addition, we propose alternative solutions for power-analysis resistant SRAM. We compare these solutions in terms of data stability, delay and side-channel resistance.