On-chip parametric test of binary-weighted R-2R ladder D/A converter and its efficiency

This paper deals with the investigation of the fault detection in separated parts of a mixed-signal integrated circuit example by implementing parametric test methods. The experimental Circuit Under Test (CUT) consisting of an 8-bit binary-weighted R-2R ladder D/A converter and additional on-chip test hardware was designed in a standard 0.35μm CMOS technology. For detection of catastrophic and parametric faults considered in different parts of the CUT, two dedicated parametric test methods: oscillation-based test technique and IDDQ monitoring were used.