Digital hardware for prime numbers generation

Prime numbers testing algorithm was implemented in specialized digital hardware. The design was coded in VHDL, verified, synthesized and loaded into FPGA. In-house developed Ethernet interface was integrated to provide external control of the computing machine from a desktop computer. Address Resolution Protocol (ARP) was added to extend this connection beyond the local area network. The device may test a single number or generate a series of prime numbers on request. The prototype was constructed and experimentally tested. Prime numbers testing unit may be replicated for higher performance and used for various cryptographic tasks.