Design & EM simulation of on-chip transformer baluns for RF power amplifiers

Guidelines and challenges in designing on-chip transformer baluns for radio frequency (RF) front-ends, especially for Power Amplifiers (PAs), are discussed. Multiple symmetric center-tapped transformer baluns are designed in Cadence Virtuoso Layout XL using 0.13μm CMOS technology and EM simulated using Sonnet 13.54. Simulation results of the final design are also verified using the transformer balun equivalent model in Cadence SpectreRF. Results show good correlation between theoretical calculations and simulation data from Sonnet. Also, comparison among our various balun designs is made on the basis of number of turns, coupling co-efficient, self-inductances, winding resistance, quality factor, phase and amplitude imbalance and area. The final design is used in a PA circuit that gives maximum 28dBm output power with an overall efficiency of 55% for an input power of 7dBm at 1.8GHz.