Title :
Verification structures for design of video processing circuits
Author :
Andrej Trost;Andrej Žemva
Author_Institution :
University of Ljubljana, Faculty of Electrical Engineering, Slovenia
fDate :
5/1/2012 12:00:00 AM
Abstract :
In the paper we present generic simulation test benches and test structures for the verification of the video processing circuits. The test benches accelerate simulation of the digital video frames in an ITU-R BT656 video format and a standard computer VGA format, which are most commonly used in our applications. The acceleration is achieved by selective stimuli in the area of the interest and selective collection of simulation results. We also present a custom FPGA based development system supporting both video formats. Several test structures were designed providing debug control and data for effective hardware verification. A video processing design case study is presented. With the presented verification methodology we are able to accelerate the design process of video processing circuits. The benefit of our approach is that it can be used with the standard programmable design tools and low cost platforms, since we do not require special software or hardware emulators. The approach can be used for the research or educational purpose.
Keywords :
"Streaming media","Field programmable gate arrays","Hardware","Synchronization","Modulation","Graphics"
Conference_Titel :
MIPRO, 2012 Proceedings of the 35th International Convention
Print_ISBN :
978-1-4673-2577-6