مرکز منطقه ای اطلاع رساني علوم و فناوري - Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

DocumentCode :

3647620

Title :

Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

Author :

S. Morvan;F. Andrieu;M. Cassé;O. Weber;N. Xu;P. Perreau;J.M. Hartmann;J.C. Barbé;J. Mazurier;P. Nguyen;C. Fenouillet-Béranger;C. Tabone;L. Tosti;L. Brévard;A. Toffoli;F. Allain;D. Lafond;B.Y. Nguyen;G. Ghibaudo;F. Boeuf;O. Fayn

Author_Institution :

CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France

fYear :

2012

fDate :

6/1/2012 12:00:00 AM

Firstpage :

111

Lastpage :

112

Abstract :

We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching I_ON,n/I_ON,p=1148/1014μA/μm drive current at I_OFF,n/I_OFF,p=55/16nA/μm leakage current (V_DD=1V) with excellent V_T-matching (A_VT <; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves I_ON,n up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.

Keywords :

"Silicon germanium","MOSFETs","Stress","Logic gates","Substrates","Silicon"

Publisher :

ieee

Conference_Titel :

VLSI Technology (VLSIT), 2012 Symposium on

ISSN :

0743-1562

Print_ISBN :

978-1-4673-0846-5

Electronic_ISBN :

2158-9682

Type :

conf

DOI :

10.1109/VLSIT.2012.6242486

Filename :

6242486

Link To Document :

https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3647620