• DocumentCode
    3647633
  • Title

    A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS

  • Author

    Dušan Stepanovic;Borivoje Nikolic

  • Author_Institution
    Berkeley Wireless Research Center, Department of Electrical Engineering and Computer Sciences, University of California, USA
  • fYear
    2012
  • fDate
    6/1/2012 12:00:00 AM
  • Firstpage
    84
  • Lastpage
    85
  • Abstract
    This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone.
  • Keywords
    "Calibration","Capacitors","Clocks","Timing","Switches","Very large scale integration","Switching circuits"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2012 Symposium on
  • Print_ISBN
    978-1-4673-0848-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2012.6243801
  • Filename
    6243801
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3647633