HIBS — Novel inter-layer bus structure for stacked architectures

Three-dimensional integrated circuit (3D IC) technology has emerged as a viable candidate to overcome the interconnections scaling and integration complexity in next generation digital system designs. In addition, combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain for 3D architectures. In recent years, through-silicon-via (TSV), employed for inter-layer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient inter-layer communication across multiple stacked layers. The bus-based organization, a hybrid between packet-switched network and a bus, is a dominant architecture for utilizing TSVs as inter-layer communication channel in 3D architectures. In this paper, we propose a novel bus structure for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration.