Ternary regenerative CMOS logic circuits with high impedance output state

Principles and possibilities for design and implementation of ternary regenerative CMOS logic circuits with high impedance output state are described and proposed in the paper. Two principles of design and concrete implementations of such logic circuits are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. All proposed and described solutions of the logic circuits have been analyzed by computer simulations. Some of simulation results confirming descriptions and conclusions are given in the paper.