Influence of assembling procedure on IC parameters

In this paper we present a new test structure, consisting of an array of piezoresistors, for analyzing the influence of the packaging procedure on the stability of silicon IC device parameters. The test structure has been mounted onto the Printed Circuit Board (PCB) substrate. Bending of the substrate with the mounted chip has been performed. The results show that a special mounting technique, leaving the sensor area free standing, significantly improves the mechanical isolation of the sensor. Finite Element Method (FEM) simulations give us the same conclusions. Finally, stress induced effects on the test structure due to the wire bonding have been measured and a change of 0.8% in offset voltage in a Wheatstone bridge configuration has been reported.