SURF algorithm implementation on FPGA

This paper describes the hardware implementation of the modified speeded-up robust features (SURF) algorithm. Field Programmable Gate Array (FPGA) is selected as a hardware platform for implementation of the modified SURF algorithm. FPGA base platform is selected to ensure features extraction in real-time video. A sliding window buffer is used to store shifted pixels of integral video frame at each clock signal. The buffer is shared with Hessian determinant, orientation and descriptor units. The interest points are searched in 8 scales in parallel by applying the non-maximal suppression. The orientation vector and simplified descriptor is computed for each feature in 6 scales. The proposed architecture is implemented using VHDL and achieves real-time orientation and descriptor calculation on 60 fps 640×480 video stream only on 25 MHz clock.