Simplification of intelligent cyclic A/D converters architecture using feedback DAC with minimal resolution

The paper presents a new concept of simplification of the architecture of so called intelligent cyclic A/D converters (IC ADCs) which enables the significant reduction of resolution of a feedback D/A sub-converter. The motivation to work on this problem results from earlier difficulties in design of a precise high-resolution feedback D/A sub-converter in practical implementation of IC ADC in CMOS technology. The modification suggested in the paper simplifies the architecture of IC ADCs and, in consequence, diminishes size, production costs, and power consumption of IC ADCs manufactured as integrated circuits or their parts. Simultaneously, the proposed solution improves the performance of IC ADC and achievable values of effective number of bits.