• DocumentCode
    3649523
  • Title

    FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard

  • Author

    Bertrand Le Gal;Christophe Jego

  • Author_Institution
    IPB / ENSEIRB-MATMECA, CNRS IMS, UMR 5218, 351 Cours de la Libé
  • fYear
    2012
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Forward Error Correction (FEC) consists in the addition of redundancy to the binary information sequence before the transmission. This redundancy allows the FEC decoder to detect and/or to correct the effects of noise and interference encountered during the transmission. An ASIP LDPC decoder compliant with DVB-T2 standard is presented in this paper.
  • Keywords
    "Decoding","Parity check codes","Computer architecture","Digital video broadcasting","Standards","Field programmable gate arrays","Plasmas"
  • Publisher
    ieee
  • Conference_Titel
    Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on
  • Print_ISBN
    978-1-4673-2089-4
  • Type

    conf

  • Filename
    6385411
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3649523