Pipelined Large Multiplier Designs on FPGAs

Large multiplication is widely used in modern cryptography systems, multimedia and signal processing applications. This paper presents three pipelined large multiplier (PLM) design methods that use specialized multiplier logic provided in modern FPGA platforms. The presented design methods provide efficient usage of symmetric multiplier resources. Also, they can be used to map a large multiplier even on a small size FPGA. The syntheses results show that a pipelined 256-bit multiplier implemented in this paper uses 15 times less DSP slices on a Virtex 5 xc5vfx100t FPGA than a monolithic multiplier mapped on the same FPGA. The trade off is a three times reduction in the speed in this specific case.