Title :
Optimizing the physical implementation of a reconfigurable cache
Author :
A. D. Santana Gil;F. J. Quiles Latorre;M. Hernandez Calvino;E. Herruzo Gómez;J. I. Benavides Benitez
Author_Institution :
Gen. Phys. Dept., Univ. of Havana, Havana, Cuba
Abstract :
The microprocessor performance is highly dependent on cache size and structure. This work presents a new design of a reconfigurable cache implemented on FPGA and based on a previous work. Advantages of the new design and the important enhancements are described and analyzed. Experimental background and tests carried out are also discussed. Tests results are favorable to the reconfigurable cache in terms of performance.
Keywords :
"Cache memory","Educational institutions","Field programmable gate arrays","Registers","Clocks","Computer architecture","Physics"
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on
Print_ISBN :
978-1-4673-2919-4
DOI :
10.1109/ReConFig.2012.6416768
