Efficient preemption of loops for dynamic HW/SW partitioning on configurable systems on chip

With the advance of high-level synthesis methodologies it has become possible to transform software tasks, typically running on a processor, to hardware tasks running on an FPGA device. Furthermore, dynamic reconfiguration techniques allow dynamic scheduling of hardware tasks on an FPGA area at runtime. The combination of these techniques allows dynamic scheduling across the hardware-software boundary. However, to interrupt and resume a task, its context has to be identified and stored. Loop bodies have to be interruptible in order to guarantee a maximum latency between interrupts. This work presents an efficient way to synchronize loop implementations between the software and the hardware world, even if control and data flows are of fundamental different nature.