Research of high-speed radar signal processing system based on OpenVPX standard

This paper proposes a new signal processing system architecture which meets OpenVPX high series bus standard, aiming to solve the problem that the embedded processing system of traditional grading sharing parallel bus cannot satisfy the intending radar´s demands such as large bus bandwidth, high-speed signal processing ability and multiprocessing nodes. The new architecture adopts the RapdiIO multi-switch network, uses the high-performance DSP and FPGA chip to realize, and makes the bandwidth of single channel bus up to 6.25GB/s. Test result shows that completing a 32K*32K complex point SAR imaging processing only needs 53.43s, it can meets signal processing needs of the future airborne radar.