• DocumentCode
    3652877
  • Title

    A phase-locked loop clock generator for a 1 GHz microprocessor

  • Author

    D.W. Boerstler;K.A. Jenkins

  • Author_Institution
    IBM Austin Res. Lab., TX, USA
  • fYear
    1998
  • Firstpage
    212
  • Lastpage
    213
  • Abstract
    The design of a fully-integrated phase-locked loop (PLL) clock generator for a 1.0 GHz microprocessor using a 1.8 V, 0.25 /spl mu/m digital CMOS6X process is described. Hardware measurements are included, showing low jitter (
  • Keywords
    "Phase locked loops","Clocks","Microprocessors","Voltage-controlled oscillators","Voltage control","Circuit noise","Phase frequency detector","Bandwidth","Laboratories","Timing"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
  • Print_ISBN
    0-7803-4766-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.1998.688088
  • Filename
    688088
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3652877