Test compression for circuits with multiple scan chains

The paper presents a test pattern compression method for circuits with a high number of parallel scan chains. It reduces test time while it keeps hardware overhead low. The decompression method is based on the continuous LFSR reseeding that is used in such a way that it enables LFSR lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. The paper discusses decompression effectiveness for different LFSR shapes, scan chain lengths and numbers of parallel LFSR inputs. We have found that it is hardware saving to use an LFSR with the state skipping instead of using a LFSR accompanied with a phase shifter. It can be designed in such a way that it uses a lower number of internal XOR gates, guarantees maximum separation between scan chains and does not introduce an extra delay on the LFSR outputs. Experimental results on benchmark circuits have shown that the presented test pattern decompression provides unreduced fault coverage and short test lengths while the hardware overhead is low comparing the designs designed with the help of nowadays industrial tools.