Hardware implementation of discrete-time neural circuit of largest/smallest signal identification

A hardware implementation in FPGA based reconfigurable computing architecture of discrete-time neural circuit that is capable of identifying the K largest/smallest of any unknown finite value N distinct inputs, where N ≤ K <; N is presented. For N competitors, such circuit is composed of N feedforward and one feedback hardlimiting neurons, that is used to determine the dynamic shift of input signals. The circuit has low computational and hardware implementation complexity, high speed of signal processing, it can process signals of any finite range, possesses signal order preserving property and does not require resetting and corresponding supervisory circuit that increases a speed of signal processing. Described the hardware implementation, based on the results of mathematical modeling KWTA Neural Network, with the FPGA-based reconfigurable computing architectures. Discussed the issues involved in using hardware blocks combining VHDL coding. Simulation example demonstrating the circuit performance is presented.