DocumentCode
3658610
Title
Power management in the Intel Xeon E5 v3
Author
Ankush Varma;Bill Bowhill;Jason Crop;Corey Gough;Brian Griffith;Dan Kingsley;Krishna Sistla
Author_Institution
Intel Inc., Santa Clara, California, United States
fYear
2015
fDate
7/1/2015 12:00:00 AM
Firstpage
371
Lastpage
376
Abstract
The Intel Xeon E5 v3 family is the latest generation of enterprise-grade, high-performance, Xeon microprocessors. It implements several new power-management technologies and features aimed at improving power/performance efficiency, increasing performance, and improving power delivery. It is the first commercial x86 processor to manage voltage/frequency optimizations on a per-core granularity. This is done by combining a) fine-grained on-die per-core voltage regulators, enabling every core on the processor to run at a different voltage, b) per-core clock management, enabling each core to run at a different frequency, and c) advanced power management algorithms for optimizing the frequency and voltage of each core based on OS requests, system utilization, on-die sensors, and silicon characteristics. The Xeon E5 v3 family also introduces a new maximum-power-draw (Pmax) management approach. This paper describes some of the technical challenges, solutions, and lessons learned during the architecture, design, and productization of this new generation of microprocessor architecture, as well as the power/performance improvements measured for server workloads.
Keywords
"Voltage control","Regulators","Microprocessors","Servers","Power demand","Rails"
Publisher
ieee
Conference_Titel
Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International Symposium on
Type
conf
DOI
10.1109/ISLPED.2015.7273542
Filename
7273542
Link To Document