Architectural error prediction using probabilistic error masking matrices

Reliability has emerged as an important design criterion due to shrinking device dimensions. To address this challenge, researchers have proposed techniques compromising the Quality-of-Service across all design abstractions. Performing cross-layer reliability-QoS trade-off is a major challenge, which requires strong understanding of the fault propagation through different design abstractions. In this paper, we propose an analytical error prediction framework, based on probabilistic error masking matrices. The prediction is performed by propagating erroneous tokens through abstract logic networks. We report detailed experiments using a RISC processor and several embedded applications. The proposed approach demonstrates significantly faster reliability evaluation compared to pure simulation-driven approach, while predicts the erroneous effects of injected faults in both architecture and application levels. Several novel techniques are also proposed to increase the accuracy of error prediction.