Work, Span, and Parallelism of Transactional Memory Programs

Recent developments indicate that after more than a decade of intensive pioneer work, both in academia and industry, transactional memory might finally become a standard part of the mainstream processors. Intel Haswell and IBM Blue Gene are first such processors indicating this trend. However, it is still not clear what would be the right performance metric and how it could be estimated and measured for a given TM program. This paper suggests that parallelism should be used as the performance metric and it proposes the method for estimating and measuring parallelism within a given TM program. In order to illustrate usage of the proposed method, we applied it to two realistic TM programs, namely Simple Bank and Race Bank. As the main result of our analysis we derived the lower and the upper bounds on parallelism for these two TM programs. Both programs have the same upper bound on parallelism, which varies from 2 to 14 when the number of read-write transactions increases from 100 to 1000, but Race Bank has better performance, because its lower bound on parallelism is constantly 1, whereas the lower bound on parallelism for Simple Bank is decreasing from 0.06 to 0.04.