• DocumentCode
    3659171
  • Title

    Fabrication and characterization of silicon nanowire ultra-thin channel poly-Si junctionless field effect transistors with a trench structure

  • Author

    Ko-Wei Lin;Mu-Shih Yeh;Min-Hsin Wu;Yung-Chun Wu

  • Author_Institution
    Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    This work demonstrates trench junctionless poly-Si thin-film transistor (JL-FET) [1] with ultra-thin body is obtained through dry etching process. JL-FET LG = 0.6μm shows excellent performance in a low drain-induced barrier lowering (DIBL), high ION/Ioff (>108), excellent gate control and reduced sensitivity to temperature in terms of VTH and SS.
  • Keywords
    "Logic gates","Fabrication","Lithography","Scanning electron microscopy","Atomic force microscopy","Transmission electron microscopy"
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2015
  • Type

    conf

  • Filename
    7275305
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3659171