Design of digital down converter using Computation sharing multiplier architecture

In the field of software defined radio, DDC plays a pivotal role in defining the optimum sampling rate without encountering any loss of information. The essential part of any DDC is the low pass filtering operation. Traditionally CIC filters are used for the design of low pass filters in the DDC which poses disadvantages in the area occupied and delay in the FPGA devices. This paper focuses on the shared resource technique for the design of the FIR filter operation. The technique involved in designing the filter is the usage of a special type of multiplier called Computation sharing multiplier(CSHM). This technique enhances the performance of the DDC and also reduces the component utilization in FPGA. Xilinx ISE is used to simulate and synthesize the design.