HDL Design Architecture for Compatible Multichannel Multi-frequency Rate SERIAL Bit Error Rate Tester (BERT) ASIC IP Core for Testing of High Speed Wireless System Products/Applications

The Aim is to Implement RTL Design Architecture for Compatible Serial Bit Error Rate Tester SOC& Multi rate Multichannel PRBS Sequence Based SERIAL BERT IP Core for High Speed Wireless Serial Communication Data Acquisition SOC Transceiver Products & Applications (3G, 4G, GPS, GSM, CDMA, WIFI, GIFI etc). Testing of Data Done By Different PRBS Pattern Sequences-2e⁷-1, 2e¹⁰-1, 2e¹⁵-1, 2e²³-1, 2e³¹-1. Basically this Serial BERT Consists of PRBS Generator Module located in the Transmitter Side & sends Pseudo Random Pulse signal is transmitted by the Serial link. Second Module is located in the receiver generate the same signal & compare with the transmitted signal, if any errors, like bit slip, bit error, Additive white Gaussian noise (AWGN), can then be detect the number of errors, and these errors are evaluated by the BERT core, estimate the error rate w.r.t number of bits. Design implementation through Soft Process Description using VHDL & Verilog HDL, Simulation & Synthesis of design done by Xilinx ISE Software Design Tool, Testing & Debugging done by FPGA Spartan Development Kit.