Design of analog subthreshold Encoded Neural Network circuit in sub-100nm CMOS

Encoded Neural Networks (ENN) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks´ (HNN) for the same number of nodes. They are thus promising for implementing large scale neural networks mimicking the functioning of the human brain. The implementation of such a network on chip requires reducing the power consumption of the nodes to the femtojoule range to compare to human brain figures. Moreover, the circuit area must be reduced as much as possible. To address these challenges, this paper proposes a subthreshold analog ENN designed for the ST 65nm CMOS process. The designed circuit accepts power supply between 0.3V and 0.86V with currents below 300nA. In a network of 30 computation nodes, it yields a 32fJ energy consumption per decoding per node. The ENN converges only 21ns after being stimulated. Finally, the node core, i.e. without synapse, has a surface area of only 9.5μm², and each synapse 3.6μm².