• DocumentCode
    3661486
  • Title

    Design of on-line division unit

  • Author

    P.K. Tu;M.D. Ercegovac

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • fYear
    1989
  • fDate
    6/11/1905 12:00:00 AM
  • Firstpage
    42
  • Lastpage
    49
  • Abstract
    A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78%.
  • Keywords
    "Algorithm design and analysis","Logic arrays","Delay","Computer science","Large scale integration","Logic design","Floating-point arithmetic"
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic, 1989., Proceedings of 9th Symposium on
  • Print_ISBN
    0-8186-8963-3
  • Type

    conf

  • DOI
    10.1109/ARITH.1989.72808
  • Filename
    72808
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3661486