Cascoded power stage with automatic dead time generation

The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.