• DocumentCode
    3662588
  • Title

    High efficiency delta-sigma transmitter architecture with gate bias modulation for wireless applications

  • Author

    Maryam Jouzdani;Fadhel M. Ghannouchi

  • Author_Institution
    iRadio Lab, Department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary, Alberta, T2N 1N4, Canada
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper proposes an efficient envelope delta-sigma based transmitter architecture with gate bias modulation for modern wireless communication systems. Using this architecture, envelope varying signals are converted to constant envelope signals. The constant envelope phase signal is up-converted and amplified utilizing high efficiency power amplifier, while the two level delta-sigma modulated envelope signal is used to switch the gate of the power amplifier. To validate the proposed technique, a prototype transmitter is implemented and evaluated. A Long-Term Evolution (LTE) uplink signal with the bandwidth of 3.84 MHz and the peak-to average power ratio (PAPR) of 7 dB is used to validate the linearity and efficiency performance of the transmitter setup. Using the LTE uplink signal, the polar architecture with modulated gate bias is able to achieve the average drain efficiency of 48% and PAE of 42% at the output power of 25.5dBm. The adjacent channel leakage ratio (ACLR) measured for this signal is less than -31dBc at 10 MHz offset from the center frequency of 2.35GHz. The measurement results are able to meet the spectrum mask without linearization techniques.
  • Keywords
    "Transmitters","Modulation","Power amplifiers","Logic gates","Noise","Prototypes","Frequency measurement"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2015.7282045
  • Filename
    7282045