• DocumentCode
    3662590
  • Title

    A new scalable fault tolerant routing algorithm for networks-on-chip

  • Author

    Hamed Sajjadi Kia;Cristinel Ababei;Sudarshan Srinivasan;Shaista Jabeen

  • Author_Institution
    Department of Electrical and Computer Engineering, North Dakota State University, Fargo, 58102 USA
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper we propose a distributed routing algorithm for networks-on-chip (NoCs) that can dynamically detect permanent failures in NoC links and recalculate routing paths using healthy links. What sets the proposed methodology apart from the previous works is that it provides a better tradeoff point between the improvement in fault tolerance and performance penalty due to the required redundancy and extra logic. An NoC prototype is implemented and simulated in Verilog-HDL to show the correct operation of the proposed adaptive routing.
  • Keywords
    "Routing","Fault tolerance","Fault tolerant systems","Hardware","Computer architecture","Ports (Computers)","Network-on-chip"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2015.7282047
  • Filename
    7282047