Digital cubic interpolation and synchronization for RF receiver using power-gated ADC

In this paper, an implementation of both interpolation and synchronization modules designed for RF receiver using power-gated ADC (PG-ADC) is presented. These modules allow lower bit error rates when demodulating non-uniformly sampled minimum-shift keying (MSK) signal. The proposed architectures are synthesized using CMOS 90 nm technology and are shown to have small occupied area (≈0.05 mm²) and low power consumption (tens to hundreds of μW). The results are detailed for several input data rates and interpolation factors.