A two-dimensional chaotic logic gate for improved computer security

In recent years the concept of chaos-based computing has emerged as a way to harness the rich state space of chaotic systems for robust computation. Potential advantages of such chaotic computational elements include improved security in the form of logic obfuscation and power analysis mitigation. For example, the chaotic nature of computation leads to a chaotic power profile that is difficult to use for side-channel attacks. In this paper, we explore the construction of chaotic logic gates based on Chua´s circuit. We propose a two-dimensional chaotic logic gate that utilizes the two state variables of Chua´s circuit to implement all possible two-input logic functions. Further, the likelihood of any logic function is shown to approach 1/16 as the evolution time of the gate is increased. Equally likely functions are beneficial from a security perspective in that the power profile and potentially the logic itself can be obfuscated from potential attackers. It is difficult to determine the effective logic function without knowledge of past states.