Efficient majority logic fault detection and correction using EG-LDPC codes for memory applications

SER is increasing for every IC process generation. Radiation induced soft errors are major concern in semiconductor memories due to technology scaling, higher integration densities and lower operating voltages. Nowadays memory cells are protected by using error correction codes. Among various multiple error correction codes ML decodable codes are suitable for memory applications due to their capability to detect a large number of errors but it requires large decoding time. In this paper a special type of low density parity check (LDPC) codes, which belongs to the family of majority logic decoding called Euclidean Geometry Low Density Parity Check (EG-LDPC) codes which detects the error in less cycle time so the decoding time is greatly reduced and also the memory accessing time also get reduced. The recent paper deals only with error detection in memories but the present paper focus on both error detection and correction by modified implementation of majority gate. The simulation results are compared with the existing techniques.