An Automated High-Level Design Framework for Partially Reconfigurable FPGAs

Modern field-programmable gate arrays (FPGAs) allow runtime partial reconfiguration (PR) of the FPGA, enabling PR benefits such as runtime adaptability and extensibility, and reduces the application´s area requirement. However, PR application development requires non-traditional expertise and lengthy design time effort. Since high-level synthesis (HLS) languages afford fast application development time, these languages are becoming increasingly popular for FPGA application development. However, widely used HLS languages, such as C variants, do not contain PR-specific constructs, thus exploiting PR benefits using an HLS language is a challenging task. To alleviate this challenge, we present an automated high-level design framework -- PaRAT (partial reconfiguration amenability test). PaRAT parses, analyzes, and partitions an application´s HLS code to generate the application´s PR architectures, which contain the application´s runtime modifiable modules and thus, allows the application´s runtime reconfiguration. Case study analysis demonstrates PaRAT´s ability to quickly and automatically generate PR architectures from an application´s HLS code.