DocumentCode :
3664167
Title :
Adaptive Reconfigurable Architecture for Image Denoising
Author :
Kartik V. Hegde;Vadiraj Kulkarni;R. Harshavardhan;S. Sumam David
Author_Institution :
Dept. of Electron. &
fYear :
2015
fDate :
5/1/2015 12:00:00 AM
Firstpage :
196
Lastpage :
201
Abstract :
In this paper, we propose an adaptive reconfigurable architecture for image denoising. First part of this paper outlines an efficient noise detection hardware for Gaussian & impulse noise detection and suitable filters for denoising. With a robust noise detection method including a novel Gaussian noise detection method, we also explore the dynamic detection of noise in an image giving adaptability to the architecture for a better quality of denoising. Proposed architecture includes a decision making unit to find out the presence of noise as well as type of the noise, based on which a suitable filter is employed during run-time. An onboard microprocessor controls the reconfiguration and dataflow. Proposed architecture is tested on Xilinx Virtex-6 FPGA with localized noise and mixed noise conditions and it gives superior performance compared to the standard filters used. High quality denoising is achieved with simple filters on a reconfigurable region utilizing smaller area and lesser hardware resources.
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium Workshop (IPDPSW), 2015 IEEE International
Type :
conf
DOI :
10.1109/IPDPSW.2015.126
Filename :
7284309
Link To Document :
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