New approach for multiple vector reduction on FPGA

Multiple vector reduction is one of the most fundamental and widely used operations in scientific computation. It is an attractive option to accelerate this computation program using FPGA as hardware accelerators. However, core operator of the vector reduction is usually floating point units which are often deeply pipelined, improper control may destroy the benefit from pipelining or impose unrealistic buffer requirements. In this paper, we propose a new approach on FPGA for multiple vector reduction. The design contributes an interleave-based vector reduction approach with high pipeline utilization. The proposed approach significantly simplifies the control units of the vector reduction operations. The sparse matrix vector multiplication is implemented as an application example in this paper.