Title :
Impact of channel line-edge roughness on junctionless FinFET
Author :
Ying Xiao;Baili Zhang;Haijun Lou;Xiaole Cui;Xinnan Lin;Lining Zhang
Author_Institution :
The Key laboratory of Integrated Microsystem, ECE, Peking university, Shenzhen graduate schoole, Shenzhen, 518055, P. R. China
fDate :
6/1/2015 12:00:00 AM
Abstract :
The impact of channel line-edge roughness (LER) on Junctionless FinFET device (JL-FinFET) is investigated by using the 3-D statistical simulation. Then the substantial influence of its narrowest width of the JL-FinFET is defined and presented. The results show that JL-FinFET is more sensitive to LER than inversion-mode FinFET. Further, the performance including the threshold voltage and on-state current is observed to be determined by the narrowest width of channel. The narrower channel has smaller on-state current and larger threshold voltage. The variations of on-state current caused by LER increase as the place of the narrowest channel width moving from drain to source. These imply that it is important to reduce the LER near the source side to suppress performance variations.
Keywords :
"FinFETs","Threshold voltage","Performance evaluation","Logic gates"
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
Print_ISBN :
978-1-4799-8362-9
DOI :
10.1109/EDSSC.2015.7285061
