DocumentCode
3664673
Title
A 14-bit 70MS/s pipeline ADC with power-efficient back-end stages
Author
Moaaz Ahmed;Fang Tang;Amine Bermak
Author_Institution
Dept. of ECE, Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong
fYear
2015
fDate
6/1/2015 12:00:00 AM
Firstpage
154
Lastpage
157
Abstract
A 14-bit SHA-less pipeline ADC based on 2.5-bit per stage architecture is proposed. Implemented in TSMC 0.18μm CMOS process, the proposed ADC achieves an ENOB of 11.34-bits and consumes 41 mW power at 70 MS/s thereby achieving an FOM of 226fJ/conversion-step which compares favorably with state-of-the-art work. The low-power consumption is attributed to the careful design of back-end stages based on a novel gain-boosting recycling folded-cascode amplifier.
Keywords
"Pipelines","Solid state circuits","Recycling","Capacitors","CMOS process","Switches","Accuracy"
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
Print_ISBN
978-1-4799-8362-9
Type
conf
DOI
10.1109/EDSSC.2015.7285073
Filename
7285073
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